1. Field of the Invention
This invention relates generally to accessing a memory over a bus, and, more particularly, to a method and an apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers.
2. Description of the Related Art
The demand for delivery of information in video and multimedia formats to households is steadily increasing. Presently installed communication technologies do not have enough bandwidth to provide adequate data transmission and new broadband cabling will take a significantly long time to reach all prospective subscriber households.
ADSL (Asymmetric Digital Subscriber Line) technology increases the digital capacity of ordinary telephone lines, by converting existing twisted-pair telephone lines into access paths for multimedia and high speed data communications. ADSL and its variants can share the same line as the telephone, because they use higher frequencies than the voice band used for typical telephone signaling protocols. The ADSL signals are combined and separated at both sides of the telephone line. At the customer's site, the splitting is done either with an external device, or it is built into an ADSL modem. Contrary to ASDL, ISDN transmits through a standard telephone system based on copper wires carrying analog voice data, a so-called switched telephone network.
The standard bus architecture found in most personal computers today is the PCI (Peripheral Component Interconnect) bus. A PCI bus is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and input/output devices of a computer system. Electrical signals are conducted over the bus so that the various components can communicate with each other. This type of bus architecture offers a simple, efficient, and cost-effective method of transmitting data.
For communication between a device and an ADSL card residing on a PCI bus, four types of transactions generally exist:                1. master write accesses from the device to the ADSL card, which is equivalent to a target read access from the perspective of the ADSL card;        2. master read accesses from the device to the ADSL card, which is equivalent to a target write access from the perspective of the ADSL card;        3. master write accesses from the ADSL card to the device, which is equivalent to a target read access from the perspective of the device card; and        4. master read accesses from the ADSL card to the device, which is equivalent to a target write access from the perspective of the device card.        
Master accesses of the ADSL card are not critical, because master writes can be posted. This leads to minimal occupation time of the PCI bus. Generally, master read accesses are targeted at fast memory. This excludes long idle times of the PCI bus while data is fetched. However, master accesses of the device to the ADSL card are critical, if the main memory of the ADSL card is slow and time-variant.
As data transmissions increase, known PCI bus transmission procedures do not show adequate operation speed, since they are too slow for present-day applications.
To fully take advantage of the ADSL technology, it is desirable to improve the accessibility of PCI cards in an ADSL environment, especially with regard to latency over a PCI bus. In a typical computing system, the most time-consuming operation is usually associated with memory access times and availability, i.e., special memories on PCI cards that have time-variant access behavior and that are not accessible by normal DMA (Direct Memory Access) transfers.
DMA is a technique for transferring data from main memory to a device without passing it through the CPU. Although DMA may periodically steal cycles from the CPU, data is transferred much faster than when the CPU is used for all data transfers. DMA uses dead time on an external bus, to perform the data transfer operations. In this way, when the processor is not accessing an expansion card, the external bus can transfer data directly to the memory. When accessing PCI card memories having time-variant access behavior, polling over the PCI bus may be required to check whether the required data is available. Furthermore, additional overhead may be attributed to setup and maintenance of control information associated with such memory accesses. In state-of-the-art systems, software overhead associated with such memory accesses is present and a high bandwidth is required. Therefore, the performance of such systems is not optimal and improved performance is desirable.
The present invention solves, or at least reduces, some or all of the aforementioned problems.